Software solutions in embedded systems allow for a flexible, portable, and cost-effective alternative to hardware designs. However, like their pure hardware counterparts, Side-channel Analysis (SCA) attacks pose a significant threat to these implementations running within embedded systems. A common countermeasure is masking, yet implementing it securely in software is challenging for third-party developers, as CPU micro-architectures are typically opaque due to intellectual property protection. As a result, developers lack awareness of micro-architectural design choices that may undermine the security of masked implementations.

To ease the generation of masked software, the tool PoMMES was presented at CHES 2024. It takes a masked C code as input and generates ARM assembly code that is in line with the Central Processing Unit ( CPU)-independent leakage model presented at CHES 2023. In particular, PoMMES proposes a constrained register allocation procedure to stay secure under the CPU-independent leakage model. The primary drawback of PoMMES, however, is its significant performance overhead, ranging from 1.3× to 3.5× compared to GCC compiled with optimization level -O0.

In this work, we show how to drastically reduce this disadvantage, effectively nullifying the performance penalty while ensuring the same security under the same conservative leakage model. We back our claims and results by evaluating 6 masked software implementations in a two-stage assessment comprising simulation-based verification and experimental power measurements on ARM Cortex-M0 and Cortex-M3 processors.