Available Thesis Topics

Below is the list of some available topics. If none of the following topics fits you, but you are interested to write your thesis at ImpSec, you may send us an email () by attaching your transcript of records. We will get back to you possibly by some other topics which may better fit to your background.

Motivation:

The application of masking in cryptographic algorithms is a widely adopted strategy for protecting implementations against side-channel attacks [1]. By employing Shamir's secret sharing scheme, each secret variable is divided into multiple shares that are independently and uniformly distributed. This approach ensures that any potential leakage is independent of the original secret. Over the years, numerous variants of masking techniques have been developed, each optimized for different objectives. However, all of these methods share a common requirement: they rely on uniform randomness for the initial sharing of secrets and, in some cases, during the computation of the masked algorithm (often referred to as online randomness). This need for randomness is particularly critical in hardware masking schemes, which consume significant amounts of random bits per cycle due to their parallel architecture. Recent research has begun to address the need for efficient hardware pseudo-random number generators (PRNGs) to supply the required randomness for masked hardware implementations [2]. However, generating randomness in software is also a non-trivial challenge.

Research Question:

Although the demand for randomness in a single clock cycle tends to be lower in software due to its sequential nature, devices may still be heavily constrained in terms of resources. Furthermore, the rapid generation of large quantities of randomness becomes even more crucial when simulating masked hardware designs for testing purposes. In these scenarios, the testing software must generate substantial amounts of randomness, which is then fed into a simulator. For an example, we refer to [3]. Accelerating the generation of randomness would not only speed up the sharing process but also enhance the overall efficiency of the simulation.

Requirements:

  • Structured way of working
  • C/C++ programming
  • Fun in optimizing code

Your Task:

To date, randomness generation has been facilitated by number-theoretic libraries, such as FLINT [4], which serve various objectives. The aim of this work is to develop a software library specifically designed for the efficient generation of random variables in arbitrary finite fields, with particular emphasis on meeting the requirements of hardware masking.

Contact:

If you are interested in this topic, please contact Nicolai Müller ().

Literature:

[1] https://www.iacr.org/archive/eurocrypt2013/78810139/78810139.pdf (opens in new tab)

[2] https://cic.iacr.org/p/1/2/4/pdf

[3] https://tches.iacr.org/index.php/TCHES/article/view/9822/9327

[4] https://flintlib.org/

Motivation:

Physical attacks, such as side-channel and fault-injection attacks, continue to pose significant threats to the security of cryptographic implementations, especially those designed with low-power and nano-scale technologies. Fortunately, countermeasures like masking and redundant computing can effectively protect against these attacks by relying on relatively simple security principles. However, applying masking to cryptographic algorithms is complex and challenging. Designers may unintentionally introduce security vulnerabilities, particularly when dealing with intricate circuits, underscoring the difficulty of achieving robust protection. Similar to verifying the correctness of hardware circuits, the proper implementation of these countermeasures can be validated by simulating the circuit repeatedly and checking if it meets specific security conditions. Therefore, efficient simulation in terms of runtime and memory consumption is crucial for evaluating the security of hardware circuits.

Research Question:

Several existing tools offer simulators for digital circuits that operate in a straightforward manner [1,2]. However, at CHES 2024, a more efficient simulator incorporating several optimizations was introduced [3]. Despite these advancements, the question remains whether further optimizations, specifically tailored to the simulation of masked circuits, are achievable.

Requirements:

  • Structured way of working
  • C/C++ or Rust programming
  • Fun in optimizing code
  • Fun in writing clean code

Your Task:

The objective of this project is to develop an efficient simulator specifically designed for masked cryptographic circuits. This involves extending the existing simulator introduced in [3] by integrating additional optimizations to enhance both runtime performance and memory efficiency, as well as incorporating features necessary for comprehensive security analysis. The primary goal is to repeatedly simulate hardware circuits to verify whether they meet specific security requirements, particularly in terms of side-channel attack resistance. The scope of the thesis also includes thoroughly testing and benchmarking the simulator using appropriate test cases and providing comprehensive documentation.

Contact:

If you are interested in this topic, please contact Nicolai Müller ().

Literature:

Motivation:

Side-channel attacks are an ubiquitous threat in embedded devices. By observing physical characteristics, e.g., the power consumption of a device, adversaries are able to recover secret data. The masking countermeasure is an effective solution against side-channel attacks. It is commonly applied on the algorithmic level, i.e., during software implementation. Unfortunately, compilers are known to (partially) remove the security of masking during compilation from high-level code to assembly code. To avoid this from happening, PoMMES-EXTRA was introduced, which implements the register allocation of a compiler backend. The register allocation is crucial for the correctness of code generation and assigns the physical registers of a CPU to the internal representation inside compilers. We added constraints to the register allocation such that the security level of the masking countermeasure does not get degraded during compilation.

Your task:

Currently PoMMES-EXTRA only supports the generation of ARMv6-M assembly instructions. However, we would like to extend the functionality of PoMMES-EXTRA to be able to generate also assembly code which is in line with the ARMv7-M ISA. Therefore your task will be to integrate the distinction and handling of different ARM instruction set architectures in PoMMES-EXTRA. Additionally you should compare the performance of PoMMES-EXTRA between the generation of ARMv6-M and ARMv7-M assembly code.

Requirements:

  • Good knowledge in C++
  • Familiarity with ARM assembly

Contact:

If you are interested in this topic, please contact Jannik Zeitschner ().

Motivation:

Protection against side-channel attacks is crucial in the context of embedded programming. Power side-channel attacks are a powerful attack vector against micro-controller and allow the adversary to retrieve secret data based on the observation of the power consumption during the execution of software. To protect implementations against side-channel attacks we apply the masking countermeasure during the implementation of software algorithms. Usually software is written in a high-level language, e.g., the C language, and then compiled to machine code. As compilers are unaware of side-channel attacks and the concept of masking, they might negatively interfere with the masking countermeasure and remove it during the compilation process. The tool PoMMES-EXTRA prevents this from happening as is places constraints on the register allocation, which is an important backend compiler pass. These constraints aim to inhibit choices during register allocation that might lower the security of masking.

Your task:

Currently only the register allocation is implemented in PoMMES-EXTRA. You should improve the code quality of the generated assembly code by implementing multiple common compiler optimizations into PoMMES-EXTRA. As there are various compiler optimizations we can discuss which optimizations might be interesting and beneficial for the code quality of the assembly code. Afterwards you should compare the performance of the unoptimized assembly code with the optimized variant.

Requirements:

  • Good knowledge in C++
  • Familiarity with ARM assembly

Contact:

If you are interested in this topic, please contact Jannik Zeitschner ().

Motivation:

Electromagnetic fault injection (EMFI) has quickly become a favored technique for inducing faults in integrated circuits (ICs) due to its non-invasiveness and precision. However, there has historically been a lack of detailed understanding of the physical mechanisms by which EMFI causes faults. Recent studies, including [1] and [2], aim to fill this gap by providing a thorough analysis of electromagnetic induction effects on ICs. These works not only explore the theoretical foundations of EMFI but also validate their models through extensive experimentation, demonstrating their effectiveness in predicting fault behavior. In addition to these theoretical approaches, more practical studies like [3] suggest that defining an adversary's strength solely by the number of faults they can inject is unrealistic. To address this limitation, two newer models have been proposed: the Random Fault Model [4] and the Generalized Random Fault Model [5]. These models define an adversary's strength by the probability that injected faults will become active, making them well-suited to account for multiple faults. As a result, these models provide a robust framework for evaluating the resilience of implementations against EMFI, enabling efficient, tool-assisted analyzes of their vulnerability to such adversaries.

Research Problem:

The objectives of this work are (1) to verify a tool currently under development and (2) to define parameters that align the tool's verification process as closely as possible with real-world conditions. This tool evaluates an implementation using the General Random Fault Model [3], simulating an EMFI (Electromagnetic Fault Injection) adversary. Your primary task is to conduct a series of EMFI attacks on both protected and unprotected implementations. Then, compare the outcomes of these practical attacks with the results generated by our tool. Based on these findings, you will propose suitable parameters to characterize various types of EMFI adversaries. If these practical attacks reveal any limitations in our tool or model, you will identify these shortcomings and recommending strategies to address them.

Requirements:

  • Structured way of working
  • Basic knowledge of Hardware Circuits
  • Familiarity with programming or tools to analyze the results (C++, Python, MATLAB)

Contact:

If you are interested, please contact Felix Uhle ().

Literature:

Motivation:

Since Kocher et al.'s early work on Side-Channel Analysis (SCA) attacks [1, 2], protecting cryptographic hardware from SCA has been a major focus of research. Numerous countermeasures, particularly masking [3] based on secret sharing [4], have been proposed to prevent information leakage. Masking [3] is popular for its straightforward security assumptions. To evaluate the strength of masked implementations, it is essential to define the capabilities of potential adversaries. One highly abstract model used for this purpose is the d-probing model [5]. Its high level of abstraction makes it widely used for proving the security of specific designs. However, designing, implementing, and verifying masked circuits remains a challenging and error-prone task, leading to many schemes being found insecure due to overlooked design flaws or incomplete adversary modeling [6, 7]. To address these issues, various tools have been proposed to detect leakage [8, 9, 10, 11, 12, 13, 14]. VERICA[12] and PROLEAD[13] are two tools that verify circuits within the d-probing model. VERICA is exact and based on Binary Decision Diagrams (BDDs), while PROLEAD utilizes a statistical approach based on simulations. The advantage of PROLEAD lies in its simulation-based strategy, which allows it to assess the security of implementations in large and complex designs, particularly in scenarios where transitions must be considered—an area that is not verifiable by VERICA.

Research Problem:

PROLEAD can evaluate large and complex circuits, such as a RISC-V ALU, enabling designers to perform tool-assisted evaluations of their designs. However, while PROLEAD effectively identifies leakage from probing sets, it does not help designers pinpoint the specific reasons for this leakage. This can be addressed by determining the minimal combination or combinations of probes that are leaking. The goal of this work is to implement an efficient strategy for identifying these minimal subsets of probes that cause leakage.

Requirements:

  • Structured way of working
  • Efficient C/C++ programming

Contact:

If you are interested, please contact Felix Uhle ().

Literature:

Motivation:

Hardware platforms play a pivotal role in establishing a root-of-trust in security applications. Reconfigurability can help maintain robust system security throughout a device’s lifecycle, comparable to software. However, physical attacks, such as side-channel and fault-injection attacks targeting cryptographic implementations, might exploit certain characteristics on the hardware level since the circuit behavior is directly influenced by the algorithm design and its realization using physical components in conventional architectures. Ensuring secure implementations on existing general puspose devices is an active and challenging research area, often incurring significant overheads in terms of area and latency. An alternative approach, though more demanding, involves designing reconfigurable platforms specifically for physically secure applications. This concept prioritizes security guarantees, potentially leading to more specialized, yet efficient solutions. One method is to base the platform design on gadget-based masking, i.e., composable subcircuits that provide formal security under a specified model. For such a custom FPGA, the associated toolchain must also be adapted to generate the appropriate bitstream.We are seeking an ambitious student eager to engage with latest research, including work that is still partly unpublished.

Your Task:

Design and implement a physically secure open-source FPGA platform with configurable security order using the FABulous framework [1]. Adapt the toolchain to automatically generate a suitable bitstream for several cryptographic implementations. Ideally, conduct a side-channel analysis by emulation of the custom platform on a real world FPGA.

Requirements:

  • Structured and organized way of working
  • Fundamental knowledge of hardware design and the F4PGA toolchain
  • Basic programming skills in VHDL / verilog and Python\
  • Familiarity with Hardware Masking is a plus

Literature:

Contact:

If you are interested in this topic, please contact Daniel Lammers ().