In this seminar we survey recent research on using reconfigurable hardware accelerators for accelerating analytical data processing. Such accelerators are being adopted as a way of overcoming the stagnation in CPU performance, because they can implement algorithms differently from traditional CPUs, breaking traditional trade-offs. The seminar will focus on Field Programmable Gate Arrays and GPUs as the main example of accelerators, but it also covers architectural trends that are propelling the rapid adoption of accelerators in datacenters and the cloud. We present guidelines for accelerator design, as well as examples of integration within full-fledged Relational Databases.
The seminar is structured as a mix of traditional lectures, paper reading exercises, and small coding projects. Its goals are:
(1) to cover the foundations of multi-core CPU architecture and the relevant trends in computer architecture / chip design, and
(2) to familiarize students with the inner working of GPUs and FPGAs and discuss their benefits in the context of analytical processing, both as an accelerator within a single node database and as part of distributed data analytics pipelines.
The prerequisite for the seminar is knowledge of C/C++, as well as, Relational Database Management Systems basics.
Prior experience with programming FPGAs is not a requirement.
|Winter Semester (22/23)
|Prof. Zsolt István, Prof. Carsten Binnig
|The kickoff meeting will be announced in Moodle (link above).